In many applications is it necessary to be able to secure and verify the integrity of data stored in a computer memory. Memory security involves protection against an adversary with physical access to the system, possessing ability to observe, tamper and/or replay the data being exchanged between a secure microprocessor and an off chip non-secure system memory. Securing commodity memory, such as dynamic random access memory (DRAM) requires accessing security metadata from memory every time off-chip data is accessed. The metadata may include counters that are used for encryption and ensuring integrity, and Message Authentication Codes (MACs) used for verifying integrity. In addition, an integrity tree data may be accessed for protection against a ‘replay’ attack. The integrity tree may be constructed as a tree of counters or a tree of MACs, with the root stored on-chip (within the secure region). In additional to using more memory for storing the metadata, the requirement to access additional memory have a negative impact of the performance of a system.
Systems for memory security and reliability may be combined, since MACs stored in memory detect tampering of memory contents can also detect random errors in memory with high probability. It has been proposed to combine MACs for detection of memory errors with chip-level parity for correction of errors, so as to achieve high levels of reliability with commodity DRAM dual inline memory modules (DIMMs).
Additional memory may be provided for storing error correction codes (ECCs). For example, server memories such as ECC-DIMMs may be provisioned with 12.5% additional storage and bus-width for error correction codes.